1. Technical Field
The present disclosure relates to a semiconductor package capable of being reduced in difference in thermal expansion with a semiconductor chip to be mounted, and improving the life of a semiconductor device, and a method for manufacturing the same.
2. Related Art
Currently, dominant semiconductor packages of CPUs or MPUs are plastic laminate packages. Particularly, with regard to a build-up structure in which on both sides of a core substrate including a glass cloth serving as a base material, metal wiring layers and insulation layers are repeatedly provided to form wirings or the like, technological innovation is accelerating. However, the difference in coefficient of thermal expansion (CTE) between Si of a semiconductor chip and a plastic package unfavorably results in the reduction of the connection reliability due to the stress concentration at the C4 connection part.
Specifically, the plastic package includes an organic material (resin), a glass cloth and a metal wire, and has a coefficient of thermal expansion of about 10 to 25 ppm/° C. In contrast, the silicon chip has a coefficient of thermal expansion of about 3 ppm/° C., and thus it is largely different in thermal expansion from the package. The reliability standards, which have been satisfied in the conventional chip size, package size, and design rule, may become impossible to satisfy the future design rule, chip size, trend for thinner layer. This conceivably causes chip cracking, cracking or peeling of the C4 connection part, breakage of an intrachip wiring layer (ILD), breakage of wirings in the package, or the like.
As the countermeasure, the following technique is proposed. That is, by employing a low elasticity structure (e.g., a coreless package) configured by eliminating the core serving as a base material, and taking out only the build-up layer, the stress occurring in the intrachip dielectric layer (ILD) due to thermal expansion of the package is controlled small. However, problems due to the low elasticity such as occurrence of the stress concentration to the connection part or wirings in the package, and occurrence of warp of the package cannot be prevented from newly occurring.
Conceivably, the thermal expansion of the semiconductor package may be reduced, and be made closer to the thermal expansion of the semiconductor chip. However, this also has a limitation for the combination of a glass cloth impregnated with a resin.
Further, in Japanese Unexamined Patent Document: JP-A-2001-7250 (FIG. 8), there is disclosed a structure in which a build-up layer is formed on a ceramic substrate. In the structure, it is expected that the thermal expansion of the build-up layer can be controlled small because of the low thermal expansion and high rigidity of the ceramic substrate. However, a ceramic substrate is necessarily required to be used and the structure cannot be applied to other substrates or coreless packages. Thus, it lacks in versatility, and hence it cannot be a general solution.